1. Field of the Invention
The present invention relates to a magnetic random access memory, and for example, to the shape of write lines in the magnetic random access memory.
2. Description of the Related Art
One of the essentials for development of memories such as magnetic random access memories (MRAM) is an increase in their degree of integration.
Peripheral circuits such as current supply circuits, selectors, or decoders are connected to wires (write lines and the like) in a memory cell array in a magnetic random access memory. The degree of integration of memory cells has recently been increasing with the development of related technologies. However, the degree of integration of the peripheral circuits does not always increase as fast as the speed of the degree of integration of memory cells. Thus, when the pitch of the peripheral circuits is larger than the arrangement pitch of the memory cells, the pitch of the peripheral circuits limits the pitch of the memory cells.
To match the pitch of the peripheral circuits with that of the memory cells, it is possible to increase one of the lengths of the peripheral circuit (for example, the lateral length of a row decoder) to reduce the other length (for example, the vertical length of the row decoder). However, this technique may increase the area of the peripheral circuit depending on the arrangement of elements constituting the peripheral circuit.
If the decoder uses a 2- or 3-input NAND circuit, it is ideal to arrange n-type transistors constituting the NAND circuit in series in order to reduce the area of the decoder. However, transistors must be arranged in parallel utilizing metal wires or the like to change the planar shape of the decoder. This increases the area of the decoder beyond that required for the series arrangement.
Further, peripheral circuits such as selectors and write current supply circuits present a similar problem. That is, a large write current is presently required, leading to the need for the large gate width of transistors used in these peripheral circuits. To meet this requirement, a plurality of transistors connected in parallel functions as one transistor having a large gate width.
For peripheral circuits such as decoders or write current supply circuits, as many circuits as the rows or columns in the memory cell array are arranged one after another. Accordingly, a reduction of the peripheral circuit size is significant for reducing the entire chip size. Thus, the above technique is inconsistent with the above requirement and is not practical.
Jpn. Pat. Appln. KOKAI Publication No. 2004-206788 discloses that electrically coupling a global address selection line shared by several subarrays to a source region of an access transistor to reduce the number of metal wires.